1. Technical Field
The present disclosure relates to a semiconductor package and, more particularly, to a semiconductor package on package having a plug-socket type wire connection.
2. Discussion of Related Art
As the technology in the electronic industry field develops, electronic parts become highly functional and compact. To keep pace with the development, a package on package (POP) technology to stack an upper package on a tower package has been developed as a package fabrication method to realize a high density package and a semiconductor package on package technology to mount a plurality of integrated circuits on a single substrate. The POP, which is increasingly used for an application processor (AP) and media, structurally includes an upper package, a tower package, and a connection unit connecting the upper package and the lower package.
FIG. 1 shows a front elevation of a general semiconductor POP 100. Referring to FIG. 1, the semiconductor POP 100 includes an upper package 10 and a lower package 20. In general, the upper package 10 includes a plurality of memory chips 12, a first printed circuit board (PCB) 14, a plurality of first connection wires 16, a first molding area 18, and a plurality of first balls 19, for example, solder balls.
The memory chips 12 are deposited on the first PCB 14. The first connection wires 16 connect the memory chips 12 and the first PCB 14. The first molding area 18 covers and protects the memory chips 12 and the first PCB 14 with an epoxy molding compound (EMC).
The first balls 19 are located under the first PCB 14 and electrically connect the upper and lower packages 10 and 20 by being combined with a ball land (not shown) formed on the upper surface of the lower package 20. In general, the lower package 20 includes a logic device 22, a second PCB 24, a plurality of second connection wires 26, a second molding area 28, and a plurality of second balls 29, for example, solder balls.
The logic device 22 is located at the center of the second PCB 24. The second molding area 28 covers and protects the logic device 22 with EMC. The second connection wires 26 connect the logic device 22 and the second PCB 24. The plurality of second balls 29 are formed on the lower surface of the second PCB 24 and electrically connect the POP 100 to a motherboard (not shown), and the POP 100 is mechanically installed on the motherboard.
As described above, the second molding area 26 covering the logic device 22 exists at the center of the lower package 20 of the POP 100. Accordingly, the solder balls cannot be arranged in an area of the upper package 10 of the POP 100 corresponding to the second molding area of the lower package 20.
Thus, as the capacity of memory chips included in the upper package 10 increases, the number of interconnections between the upper and lower packages 10 and 20 increases The number of solder balls arranged in the upper package 10, however, is limited by the structure of the lower package 20. Also, the conventional POP 100 has a problem regarding the solder ball reliability of the contact of the solder balls between the upper and lower packages 10 and 20.
The thermal expansion coefficients of the first PCB 14, the first solder balls 19 located at the lower surface of the first PCB 14, and the second PCB 24 including the ball land (not shown) that the first solder balls 19 contact are different from one another. Thus, when the lower package 20 installed on the motherboard is stressed, because the thermal expansion coefficients of the first PCB 14, the first solder balls 19, and the second PCB 24 are different from one another, cracks may be generated in the first solder balls 19, which causes defects in the end products, for example, a motherboard or a memory module.
Therefore, there is a demand for the structure of a connector connecting the upper and lower packages of the POP that can increase the number of interconnections of the POP and reduce an adverse effect from the motherboard caused by stress.